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copyright ? 2006 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this specifcation and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services described herein. customers are advised to obtain the latest version of this device specifcation before relying on any published information and before placing orders for products. IS66WV51216ALL is66wv51216bll integrated silicon solution, inc. www.issi.com 1 rev. a 12/02/09 8mb low voltage, ultra low power pseudo cmos static ram features ? high-speed access time: 55ns ? cmos low power operation C mw (typical) operating C w (typical) cmos standby ? single power supply C 1.7v--1.95v v d d (66wv51216all) (70ns) C 2.5v--3.6v v d d (66wv51216bll) (55ns) ? three state outputs ? data control for upper and lower bytes ? industrial temperature available ? lead-free available description the issi IS66WV51216ALL/bll is a high-speed, 8m bit static rams organized as 512k words by 16 bits. it is fabricated using issi 's high-performance cmos technology. this highly reliable process coupled with innovative circuit design techniques, yields high-performance and low power consumption devices. when cs1 is high (deselected) or when cs2 is low (deselected) or when cs1 is low , cs2 is high and both lb and ub are high, the device assumes a standby mode at which the power dissipation can be reduced down with cmos input levels. easy memory expansion is provided by using chip enable and output enable inputs. the active low write enable (we) controls both writing and reading of the memory. a data byte allows upper byte (ub) and lower byte (lb) access. the IS66WV51216ALL/bll is packaged in the jedec standard 48-pin mini bga (6mm x 8mm) and 44-pin tsop (type ii). the device is aslo available for die sales. functional block diagram january 2010 a0-a18 cs1 oe we 512k x 16 memory array decoder column i/o control circuit gnd v dd i/o data circuit i/o0-i/o7 lower byte i/o8-i/o15 upper byte ub lb cs2
2 integrated silicon solution, inc. www.issi.com rev. a 12/02/09 IS66WV51216ALL is66wv51216bll pin configurations: 512 k x 16 48-pin mini bga (6mm x 8mm) pin descriptions a0-a18 address inputs i/o0-i/o15 data inputs/outputs cs1, cs2 chip enable input oe output enable input we write enable input lb lower-byte control (i/o0-i/o7) ub upper-byte control (i/o8-i/o15) nc no connection v d d power gnd ground 1 2 3 4 5 6 a b c d e f g h lb oe a0 a1 a2 cs2 i/o 8 ub a3 a4 cs1 i/o 0 i/o 9 i/o 10 a5 a6 i/o 1 i/o 2 gnd i/o 11 a17 a7 i/o 3 v dd` v dd i/o 12 nc a16 i/o 4 gnd i/o 14 i/o 13 a14 a15 i/o 5 i/o 6 i/o 15 nc a12 a13 we i/o 7 a18 a8 a9 a10 a11 nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 a4 a3 a2 a1 a0 cs1 i/o0 i/o1 i/o2 i/o3 v dd gnd i/o4 i/o5 i/o6 i/o7 we a16 a15 a14 a13 a12 a5 a6 a7 oe ub lb i/o15 i/o14 i/o13 i/o12 gnd v dd i/o11 i/o10 i/o9 i/o8 a18 a8 a9 a10 a11 a17 44-pin tsop (type ii)
integrated silicon solution, inc. www.issi.com 3 rev. a 12/02/09 IS66WV51216ALL is66wv51216bll truth table i/o pin mode we cs1 cs2 oe lb ub i/o0-i/o7 i/o8-i/o15 v d d current not selected x h x x x x high-z high-z i s b 1 , i s b 2 x x l x x x high-z high-z i s b 1 , i s b 2 x x x x h h high-z high-z i s b 1 , i s b 2 output disabled h l h h l x high-z high-z i c c h l h h x l high-z high-z i c c read h l h l l h d o u t high-z i c c h l h l h l high-z d o u t h l h l l l d o u t d o u t write l l h x l h d i n high-z i c c l l h x h l high-z d i n l l h x l l d i n d i n operating range (v d d ) range ambient temperature (70ns) (55ns) (70ns) commercial 0c to +70c 1.7v - 1.95v 2.5v - 3.6v industrial C40c to +85c 1.7v - 1.95v 2.5v - 3.6v automotive C40c to +105c 2.5v-3.6v
4 integrated silicon solution, inc. www.issi.com rev. a 12/02/09 IS66WV51216ALL is66wv51216bll dc electrical characteristics (over operating range) symbol parameter test conditions v d d min. max. unit v o h output high voltage i o h = -0.1 ma 1.7-1.95v 1.4 v i o h = -1 ma 2.5-3.6v 2.2 v v o l output low voltage i o l = 0.1 ma 1.7-1.95v 0.2 v i o l = 2.1 ma 2.5-3.6v 0.4 v v i h input high voltage 1.7-1.95v 1.4 v d d + 0.2 v 2.5-3.6v 2.2 v d d + 0.3 v v i l (1) input low voltage 1.7-1.95v C0.2 0.4 v 2.5-3.6v C0.2 0.6 v i l i input leakage gnd v i n v d d C1 1 a i l o output leakage gnd v o u t v d d , outputs disabled C1 1 a notes: 1. v i l (min.) = C1.0v for pulse width less than 10 ns. absolute maximum ratings (1) symbol parameter value unit v t e r m terminal voltage with respect to gnd C0.2 to v d d +0.3 v t b i a s temperature under bias C40 to +85 c v d d v d d related to gnd C0.2 to +3.8 v t s t g storage temperature C65 to +150 c p t power dissipation 1.0 w note: 1. stress greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specifcation is not implied. exposure to absolute maximum rat - ing conditions for extended periods may affect reliability.
integrated silicon solution, inc. www.issi.com 5 rev. a 12/02/09 IS66WV51216ALL is66wv51216bll ac test conditions parameter 1.7v-1.95v 2.5v-3.6v (unit) (unit) input pulse level 0.4v to v d d -0.2 0.4v to v d d -0.3v input rise and fall times 5 ns 5ns input and output timing v r e f v r e f and reference level output load see figures 1 and 2 see figures 1 and 2 ac test loads figure 1 figure 2 1.7v - 1.95v 2.5v - 3.6v r1(?) 3070 1029 r2(?) 3150 1728 v r e f 0.9v 1.4v v t m 1.8v 2.8v capacitance (1) symbol parameter conditions max. unit c i n input capacitance v i n = 0v 8 pf c o u t input/output capacitance v o u t = 0v 10 pf note: 1. tested initially and after any design or process changes that may affect these parameters. r1 5 pf including jig and scope r2 output vtm r1 30 pf including jig and scope r2 output vtm
6 integrated silicon solution, inc. www.issi.com rev. a 12/02/09 IS66WV51216ALL is66wv51216bll 1.7v-1.95v power supply characteristics (1) (over operating range) symbol parameter test conditions max. unit 70ns i c c v d d dynamic operating v d d = max., com. 20 ma supply current i o u t = 0 ma, f = f m a x ind. 25 all inputs 0.4v auto. 30 or v d d C 0.2v typ. (1) i c c 1 operating supply v d d = max., cs1 = 0.2v com. 4 ma current we = v d d C 0.2v ind. 4 cs2 = v d d C 0.2v, f = 1 m h z auto. 10 i s b 1 ttl standby current v d d = max., com. 0.6 ma (ttl inputs) v i n = v i h or v i l ind. 0.6 cs1 = v i h , cs2 = v i l , a u t o . 1 f = 1 mh z or ulb control v d d = max., v i n = v i h or v i l cs1 = v i l , f = 0, ub = v i h , lb = v i h i s b 2 cmos standby v d d = max., com. 100 a current (cmos inputs) cs1 v d d C 0.2v, ind. 120 cs2 0.2v, auto. 150 v i n v d d C 0.2v, or typ. (1) v i n 0.2v, f = 0 or ulb control v d d = max., cs1 = v i l , cs2=v i h v i n v d d C 0.2v, or v i n 0.2v, f = 0; ub / lb = v d d C 0.2v note:. 1. typical values are measured at v d d = 1.8v, t a = 25 o c and not 100% tested.
integrated silicon solution, inc. www.issi.com 7 rev. a 12/02/09 IS66WV51216ALL is66wv51216bll 2.5v-3.6v power supply characteristics (1) (over operating range) symbol parameter test conditions max. unit 55ns i c c v d d dynamic operating v d d = max., com. 25 ma supply current i o u t = 0 ma, f = f m a x ind. 28 all inputs 0.4v auto. 35 or v d d C 0.3v typ. (2) 15 i c c 1 operating supply v d d = max., cs1 = 0.2v com. 5 ma current we = v d d C 0.2v ind. 5 cs2 = v d d C 0.2v, f = 1 m h z a u t o . 10 i s b 1 ttl standby current v d d = max., com. 0.6 ma (ttl inputs) v i n = v i h or v i l ind. 0.6 cs1 = v i h , cs2 = v i l , a u t o . 1 f = 1 mh z or ulb control v d d = max., v i n = v i h or v i l cs1 = v i l , f = 0, ub = v i h , lb = v i h i s b 2 cmos standby v d d = max., com. 100 a current (cmos inputs) cs1 v d d C 0.2v, ind. 130 cs2 0.2v, auto. 150 v i n v d d C 0.2v, or typ. (2) 75 v i n 0.2v, f = 0 or ulb control v d d = max., cs1 = v i l , cs2=v i h v i n v d d C 0.2v, or v i n 0.2v, f = 0; ub / lb = v d d C 0.2v note: 1. at f = f m a x , address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. typical values are measured at v d d = 3.0v, t a = 25 o c and not 100% tested.
8 integrated silicon solution, inc. www.issi.com rev. a 12/02/09 IS66WV51216ALL is66wv51216bll data valid previous data valid t aa t oha t oha t rc d q0-d15 address ac waveforms read cycle no. 1 (1,2) (address controlled) (cs1 = oe = v i l , cs2 = we = v i h , ub or lb = v i l ) read cycle switching characteristics (1) (over operating range) 55 ns 70 ns symbol parameter min. max. min. max. unit t r c read cycle time 55 70 ns t a a address access time 55 70 ns t o h a output hold time 10 10 ns t a c s 1/ t a c s 2 cs1/cs2 access time 55 70 ns t d o e oe access time 25 35 ns t h z o e (2) oe to high-z output 20 25 ns t l z o e (2) oe to low-z output 5 5 ns t h z c s 1/ t h z c s 2 (2) cs1/cs2 to high-z output 0 20 0 25 ns t l z c s 1/ t l z c s 2 (2) cs1/cs2 to low-z output 10 10 ns t b a lb, ub access time 55 70 ns t h z b lb, ub to high-z output 0 20 0 25 ns t l z b lb, ub to low-z output 0 0 ns notes: 1. test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9v/1.5v, input pulse levels of 0.4 to v d d -0.2v/0.4v to v d d -0.3v and output loading specifed in figure 1. 2. tested with the load in figure 2. transition is measured 100 mv from steady-state voltage. not 100% tested.
integrated silicon solution, inc. www.issi.com 9 rev. a 12/02/09 IS66WV51216ALL is66wv51216bll t rc t oha t aa t doe t lzoe t ace1/ t ace2 t lzce1/ t lzce2 t hzoe high-z data valid t hzcs1/ t hzcs1 address oe cs1 cs2 dout lb , ub t hzb t ba t lzb ac waveforms read cycle no. 2 (1,3) ( cs1, cs2, oe, and ub/lb controlled) notes: 1. we is high for a read cycle. 2. the device is continuously selected. oe, cs1, ub, or lb = v i l . cs2=we=v i h . 3. address is valid prior to or coincident with cs1 low transition.
10 integrated silicon solution, inc. www.issi.com rev. a 12/02/09 IS66WV51216ALL is66wv51216bll notes: 1. write is an internally generated signal asserted during an overlap of the low states on the cs1 , cs2 and we inputs and at least one of the lb and ub inputs being in the low state. 2. write = (cs1) [ (lb) = (ub) ] (we). ac waveforms write cycle no. 1 (1,2) (cs1 controlled, oe = high or low) data-in vali d data undefined t wc t scs1 t scs2 t aw t ha t pwe t hzwe high-z t lzwe t sa t sd t hd address cs1 cs2 we dout din lb, ub t pwb write cycle switching characteristics (1,2) (over operating range) 55 ns 70 ns symbol parameter min. max. min. max. unit t w c write cycle time 55 70 ns t s c s 1/ t s c s 2 cs1/cs2 to write end 45 60 ns t a w address setup time to write end 45 60 ns t h a address hold from write end 0 0 ns t s a address setup time 0 0 ns t p w b lb, ub valid to end of write 45 60 ns t p w e (4) we pulse width 45 60 ns t s d data setup to write end 25 30 ns t h d data hold from write end 0 0 ns t h z w e (3) we low to high-z output 20 30 ns t l z w e (3) we high to low-z output 5 5 ns notes: 1. test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9v/1.5v, input pulse levels of 0.4 to v d d -0.2v/0.4v to v d d -0.3v and output loading specifed in figure 1. 2. the internal write time is defned by the overlap of cs1 low, cs2 high and ub or lb, and we low. all signals must be in valid states to initiate a write, but any one can go inactive to terminate the write. the data input setup and hold timing are referenced to the rising or falling edge of the signal that terminates the write. 3. tested with the load in figure 2. transition is measured 100 mv from steady-state voltage. not 100% tested. 4. t p w e > t h z w e + t s d when oe is low.
integrated silicon solution, inc. www.issi.com 11 rev. a 12/02/09 IS66WV51216ALL is66wv51216bll write cycle no. 2 (we controlled: oe is high during write cycle) write cycle no. 3 (we controlled: oe is low during write cycle) data-in vali d data undefined t wc t scs1 t scs2 t aw t ha t pwe t hzwe high-z t lzwe t sa t sd t hd address oe cs1 cs2 we lb, ub dout din data-in vali d data undefined t wc t scs1 t scs2 t aw t ha t pwe t hzwe high-z t lzwe t sa t sd t hd address oe cs1 cs2 we lb, ub dout din
12 integrated silicon solution, inc. www.issi.com rev. a 12/02/09 IS66WV51216ALL is66wv51216bll write cycle no. 4 (ub/lb controlled) data undefined t wc address 1 address 2 t wc high-z t pbw word 1 low word 2 t hd t sa t hzwe address cs1 ub, lb we d out d in oe data in valid t lzwe t sd t pbw data in valid t sd t hd t sa t ha t ha ub_cswr4.eps high cs2
integrated silicon solution, inc. www.issi.com 13 rev. a 12/02/09 IS66WV51216ALL is66wv51216bll please avoid address change for less than t r c during the cycle time longer than 15 ms (figure 1). figure 2 & 3 provide work around solution for this issue.
14 integrated silicon solution, inc. www.issi.com rev. a 12/02/09 IS66WV51216ALL is66wv51216bll IS66WV51216ALL industrial range: -40c to +85c voltage range: 1.7v to 1.95v speed (ns) order part no. package 70 IS66WV51216ALL-70tli tsop-ii, lead-free IS66WV51216ALL-70bli mini bga (6mm x 8mm), lead-free is66wv51216bll industrial range: -40c to +85c voltage range: 2.5v to 3.6v speed (ns) order part no. package 55 is66wv51216bll-55tli tsop-ii, lead-free is66wv51216bll-55bli mini bga (6mm x 8mm), lead-free
integrated silicon solution, inc. www.issi.com 15 rev. a 12/02/09 IS66WV51216ALL is66wv51216bll 2. dimension d and e1 do not include mold protrusion. 3. dimension b does not include dambar protrusion/intrusion. 1. controlling dimension : mm note : 06/04/2008 package outline
16 integrated silicon solution, inc. www.issi.com rev. a 12/02/09 IS66WV51216ALL is66wv51216bll 2. reference document : jedec mo-207 1. controlling dimension : mm . note : 08/12/2008 package outline

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